People

Dr Server Kasap

Senior Research Officer
School of Computer Science and Electronic Engineering (CSEE)
Dr Server Kasap

Publications

Journal articles (9)

Kasap, S., Weber Wachter, E., Zhai, X., Ehsan, S. and McDonald-Maier, K., (2020). Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs. IEEE Access. 8, 28646-28658

Kasap, S. and Redif, S., (2019). High-Performance System-on-Chip-Based Accelerator System for Polynomial Matrix Multiplications. Circuits, Systems, and Signal Processing. 38 (12), 5755-5785

Carcenac, M., Redif, S. and Kasap, S., (2017). GPU parallelization of the sequential matrix diagonalization algorithm and its application to high-dimensional data. The Journal of Supercomputing. 73 (8), 3603-3634

Redif, S. and Kasap, S., (2015). Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (3), 454-465

Kasap, S. and Redif, S., (2014). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22 (3), 522-536

Redif, S. and Kasap, S., (2013). Parallel algorithm for computation of second-order sequential best rotations. International Journal of Electronics. 100 (12), 1646-1651

Kasap, S. and Benkrid, K., (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA-Based Supercomputer. Journal of Computers. 7 (6), 1312-1328

Kasap, S. and Benkrid, K., (2011). High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19 (5), 796-808

Kasap, S., Benkrid, K. and Liu, Y., (2008). Design and Implementation of an FPGA-based Core for Gapped BLAST Sequence Alignment with the Two-Hit Method.. Engineering Letters. 16, 443-452

Conferences (10)

Wachter, EW., Kasap, S., Zhai, X., Ehsan, S. and McDonald-Maier, K., (2020). Survey of Lockstep based Mitigation Techniques for Soft Errors in Embedded Systems

Kasap, S. and Redif, S., (2014). Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

Kasap, S. and Redif, S., (2013). FPGA implementation of a second-order convolutive blind signal separation algorithm

Kasap, S. and Redif, S., (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm

Kasap, S. and Benkrid, K., (2011). A high performance implementation for Molecular Dynamics simulations on a FPGA supercomputer

Kasap, S. and Benkrid, K., (2009). A high performance FPGA-based core for phylogenetic analysis with Maximum Parsimony method

Liu, Y., Benkrid, K., Benkrid, A. and Kasap, S., (2009). An FPGA-Based Web Server for High Performance Biological Sequence Alignment

Kasap, S., Benkrid, K. and Liu, Y., (2009). A high performance fpga-based implementation of position specific iterated blast

Kasap, S., Benkrid, K. and Liu, Y., (2008). High performance FPGA-based core for BLAST sequence alignment with the two-hit method

Benkrid, K., Velentzas, P. and Kasap, S., (2008). A High Performance Reconfigurable Core for Motif Searching Using Profile HMM

Contact

server.kasap@essex.ac.uk

Location:

Colchester Campus