University of Essex

CE869-7-SP-CO:
High Level Logic Design

The details

Year: 2023/24

Department: Computer Science and Electronic Engineering (School of)

Campus: Colchester Campus

Term: Spring

Level: Postgraduate: Level 7

Status: Current

Start date: Monday 15 January 2024

End date: Friday 22 March 2024

Credits: 15

Last updated: 07 November 2023

Requisites for this module

Pre-requisites: (none)

Co-requisites: (none)

Pre and / or co-requisites: (none)

Prohibited modules: CE339

Key module (requisite for): (none)

Key module for

MSC H61212 Computer Engineering,
MSC H612CH Computer Engineering

Module description

Students are not permitted to undertake this module if they have done the equivalent module of CE339 at UG level on a CSEE undergraduate course. This is because it cannot count towards your course credits. Please contact the CSEE School Office for specific advice on your module choices.

Digital systems are in virtually all devices we interact with: from consumer electronics, to biomedical applications and automotive industry. Digital technology is evolving so rapidly that engineers need rapid-prototyping software and hardware tools that allow them to explore and test an implementation before moving to the production.

In this module, learners will gain fundamental circuit design and verification skills by using an industry-standard hardware description language to program field-programmable gate arrays (FPGAs). The learning process is experience-oriented so that hands-on practice in designing embedded systems as well as theoretical background is acquired during the course.

Note: This module assumes that students are already familiar with combinatorial and sequential logic elements.

Module aims

The aim of this module is to study the application of digital systems to consumer electronics. With the rapid pace of change, digital design needs to be adaptive and fast to implement. Therefore an industry standard hardware description language (HDL) will be used in this module to program field-programmable gate arrays (FPGAs).

Students are not permitted to undertake this module if they have done the equivalent module of CE339 at UG level on a CSEE undergraduate course. This is because it cannot count towards your course credits. Please contact the CSEE School Office for specific advice on your module choices.

Module learning outcomes

After completing this module, students will be expected to be able to:

1. Explain the process of automated digital system design using hardware description languages
2. Design and implement digital systems using hardware description languages
3. Test an HDL design using simulation and FPGA platform
4. Demonstrate an understanding of microprocessor design

Module information

Outline Syllabus:

Introduction to behavioural, data flow, and structural modelling of HDL.
Basic HDL code structure and syntax.
Review of combinational and sequential logic. Definition of concurrent and sequential modes.
Concurrent and sequential statements in HDL.
Systematic review of HDL's data types and data attributes.
Review of fundamental concepts related to finite state machines and the corresponding HDL coding techniques.
Review and evaluation of hardware technologies (FPGAs, ASICs, microprocessors, microcontrollers, DSPs).
Introduction to the internal architecture and functioning of a microprocessor.
Importance of testing complex designs and validating the design prior to fabrication.

Learning and teaching methods

Labs and Lectures

Bibliography

Pedroni, V.A. and Pedroni, V.A. (2010) Circuit design and simulation with VHDL. 2nd ed. Cambridge, MA: MIT Press. Available at: https://app.kortext.com/Shibboleth.sso/Login?entityID=https://idp0.essex.ac.uk/shibboleth&target=https://app.kortext.com/borrow/149745.
Hwang, E. (2018) Digital Logic and Microprocessor Design with Interfacing. 2nd edition. Australia: Cengage Learning. Available at: https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=2638772.
Kenneth L. Short (2008) VHDL for Engineers. Prentice Hall. Available at: https://ebookcentral.proquest.com/lib/universityofessex-ebooks/detail.action?docID=5174432.
‘Learning FPGA development’ (no date). Available at: https://www.linkedin.com/learning/learning-fpga-development/demo-system-for-the-intel-platform?u=51088249.

The above list is indicative of the essential reading for the course.
The library makes provision for all reading list items, with digital provision where possible, and these resources are shared between students.
Further reading can be obtained from this module's reading list.

Assessment items, weightings and deadlines

Coursework / exam	Description	Coursework weighting
Coursework	Progress Test 1	20%
Coursework	Progress Test 2	20%
Coursework	Assignment 1 - Project 1: HDL Introductory Design	20%
Coursework	Assignment 2 - Project 2: HDL Advanced Design	40%

Exam format definitions

Remote, open book: Your exam will take place remotely via an online learning platform. You may refer to any physical or electronic materials during the exam.
In-person, open book: Your exam will take place on campus under invigilation. You may refer to any physical materials such as paper study notes or a textbook during the exam. Electronic devices may not be used in the exam.
In-person, open book (restricted): The exam will take place on campus under invigilation. You may refer only to specific physical materials such as a named textbook during the exam. Permitted materials will be specified by your department. Electronic devices may not be used in the exam.
In-person, closed book: The exam will take place on campus under invigilation. You may not refer to any physical materials or electronic devices during the exam. There may be times when a paper dictionary, for example, may be permitted in an otherwise closed book exam. Any exceptions will be specified by your department.

Your department will provide further guidance before your exams.

Overall assessment

Coursework	Exam
100%	0%

Reassessment

Coursework	Exam
100%	0%

Module supervisor and teaching staff

Supervisor: Dr Wenqiang Yi, email: w.yi@essex.ac.uk.

Teaching staff: Dr Wenqiang Yi

Contact details: School Office, email: csee-schooloffice (non-Essex users should add @essex.ac.uk to create full e-mail address), Telephone 01206 872770

Availability

Available to incoming Essex Abroad / Exchange students: Yes

Available to Outside Option: No

Available to Audit: No

External examiner

Name: Dr Marios Angelopoulos

Institution: Bournemouth University

Academic role: Principal Academic

Name: Dr Dimitrios Kanoulas

Institution: UCL

Academic role: Associate Professor

Resources

Teaching materials: Available via Moodle

Lecture recording: Of 148 hours, 18 (12.2%) hours available to students:
128 hours not recorded due to service coverage or fault;
2 hours not recorded due to opt-out by lecturer(s), module, or event type.

Further information

Department website: Computer Science and Electronic Engineering (School of)

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Module Directory

CE869-7-SP-CO:High Level Logic Design